Scalable Shared-Memory Multiprocessing
Scalable Shared-Memory Multiprocessing
Technology-Driven, Highly-Scalable Dragonfly Topology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Low-Cost 20 Gbps Digital Test Signal Synthesis Using SiGe and InP Logic
Journal of Electronic Testing: Theory and Applications
Extending a DWDM Optical Network Test System to 12 Gbps x4 Channels
Journal of Electronic Testing: Theory and Applications
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
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The architecture proposed here reduces remote memory access latency by increasing connectivity and maximizing channel availability for remote communication. It also provides efficient and fast unicast, multicast, and broadcast capabilities, using a combination of aggressively designed multiplexing techniques. Simulations show that this architecture provides excellent interconnect support for a highly scalable, high-bandwidth, low-latency network.