Domain Specific Reconfigurable Architecture of Turbo Decoder Optimized for Short Distance Wireless Communication

Authors:
Imran Ahmed;Tughrul Arslan;Sajid Baloch;Ian Underwood;Robin Woodburn
Affiliations:
University of Edinburgh, UK/ Institute for System Level Integration, UK/ MED Ltd., UK;University of Edinburgh, UK/ Institute for System Level Integration, UK;University of Edinburgh, UK/ Institute for System Level Integration, UK/ MED Ltd., UK;MED Ltd., UK;MED Ltd., UK
Venue:
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Year:
2005

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Abstract

This paper describes low power, reconfigurable architectures for Turbo Decoder. Currently most of the reconfigurable solutions in research target reconfiguration between different convolution based decoders for example Viterbi-Sova or Sova-LogMap. The reconfigurable Turbo decoder array presented in this paper not only provides flexibility to choose between different constraint lengths, frame lengths and code rates but also different levels of quantization. Similarly, dynamic or static mapping of different algorithms can be done to meet various performance constraints in terms of reduced power, improved speed and different levels of error correction. The architecture can support channel decoding for most of the current communication systems.