Experiences with Soft-Core Processor Design

Authors:
Franjo Plavec;Blair Fort;Zvonko G. Vranesic;Stephen D. Brown
Affiliations:
University of Toronto, Canada;University of Toronto, Canada;University of Toronto, Canada;University of Toronto, Canada
Venue:
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Year:
2005

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Abstract

Soft-core processors exploit the flexibility of Field Programmable Gate Arrays (FPGAs) to allow a system designer to customize the processor to the needs of a target application. This paper describes the UT Nios implementation of Altera's Nios architecture. A benchmark set appropriate for soft-core processors is defined. Using the benchmark set, the performance of UT Nios is explored and compared with the commercial implementation.