Complexity-effective superscalar processors
Proceedings of the 24th annual international symposium on Computer architecture
The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
A high-speed dynamic instruction scheduling scheme for superscalar processors
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Energy Efficient Comparators for Superscalar Datapaths
IEEE Transactions on Computers
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The instruction queue is a critical component and performance bottleneck in superscalar microprocessors. Conventional designs use physical register identifiers to wake up instructions. This paper proposes decoupling the tags for instruction wakeup from the tags for physical register access, thus increasing the design space of the instruction queue by encoding its operand tags. Two coding methods have been developed. One uses a linear code to increase the Hamming distance between tags, reducing the tag match delay by more than 50% and achieving 12% improvement in the total wakeup/select delay for TSMC 0.18mm technology at 1.8v. The second method uses one-hot code to encode the operand tag, removing the tag OR and tag read operations from the wakeup/select loop. For a 32-entry instruction queue, 15% reduction in the wakeup/select loop has been achieved. Furthermore, one-hot code also removes the dissipation-on-mismatch in the wakeup logic, significantly reducing the dynamic power consumption of the instruction queue.