Accelerating Statistical Texture Analysis with an FPGA-DSP Hybrid Architecture

Authors:
F. Ibarra Pico;S. Cuenca Asensi;V. Corcoles
Affiliations:
Universidad de Alicante;Universidad de Alicante;Universidad de Alicante
Venue:
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Year:
2001

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An FPGA implementation for texture analysis considering the real-time requirements of vision-based systems

ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications

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Abstract

Nowadays, most image processing systems are implemented using either MMX-optimized software libraries or, when time requirements are limited, expensive high performance DSP-based boards. In this paper we present a texture analysis co-processor concept that permits the efficient hardware implementation of statistical feature extraction, and hardware-software codesign to achieve high-performance low-cost solutions. We propose a hybrid architecture based on FPGA chips, for massive data processing, and digital signal processor (DSP) for floating-point computations. In our preliminary trials with test images, we achieved sufficient performance improvements to handle a wide range of real-time applications.