Code sharing among states for stack-caching interpreter

  • Authors:
  • Jinzhan Peng;Gansha Wu;Guei-Yuan Lueh

  • Affiliations:
  • Intel Corporation;Intel Corporation;Intel Corporation

  • Venue:
  • Proceedings of the 2004 workshop on Interpreters, virtual machines and emulators
  • Year:
  • 2004

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Abstract

Interpretation has salient merits of simplicity, portability and small footprint but comes with a price of poor performance. Stack caching is a technique to build a high-performance interpreter by keeping source and destination operands of instructions in registers so as to reduce memory accesses involved during interpretation. One drawback of stack caching is that an instruction may have multiple ways to perform interpretation depending on which registers source operands reside in, resulting in code explosion as well as deterioration of code maintainability. This paper presents a code sharing mechanism that achieves performance as efficient as the stack-caching interpreter and in the meantime keeps the code size as compact as general threaded interpreters. Our results show that our approach outperforms a threaded interpreter by an average of 13.6% and the code size increases by only 1KB (~3%).