Smart debugging software architectural design in SDL

  • Authors:

  • W. Eric Wong;Tatiana Sugeta;Yu Qi;Jose C. Maldonado

  • Affiliations:

  • Department of Computer Science, University of Texas at Dallas, Richardson, TX;Department of Computer Science, University of Texas at Dallas, Richardson, TX and University of Sao Paulo at Sao Carlos;Department of Computer Science, University of Texas at Dallas, Richardson, TX;Department of Computer Science, University of Sao Paulo at Sao Carlos, Sao Carlos, SP, Brazil

  • Venue:
  • Journal of Systems and Software - Special issue: Computer software & applications
  • Year:
  • 2005

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Abstract

Statistical data show that it is much cheaper to fix software bugs at the early design stage than the late stage of the development process where the final system has already been implemented and integrated together. The use of slicing and execution histories as an aid in software debugging is well established for programming languages like C and C++; however, it is rarely applied in the field of software specification for designs. We propose a solution by applying the technology at source code level to debugging software designs represented in a high-level specification and description language such as SDL. More specifically, we extend execution slice-based heuristics from source code-based debugging to the software design specification level. Suspicious locations in an SDL specification are prioritized based on their likelihood of containing faults. Locations with a higher priority should be examined first rather than those with a lower priority as the former are more suspicious than the latter, i.e., more likely to contain the faults. A debugging tool, SmartDSDL, with user-friendly interfaces was developed to support our method. An experiment is reported to demonstrate the feasibility of using our method to effectively debug an architectural design.