Managing memory access latency in packet processing

Authors:
Jayaram Mudigonda;Harrick M. Vin;Raj Yavatkar
Affiliations:
University of Texas at Austin;University of Texas at Austin;Intel Corporation
Venue:
SIGMETRICS '05 Proceedings of the 2005 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Year:
2005

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Abstract

In this study, we refute the popular belief [1,2] that packet processing does not benefit from data-caching. We show that a small data-cache of 8KB can bring down the packet processing time by much as 50-90%, while reducing the off-chip memory bandwidth usage by about 60-95%. We also show that, unlike general-purpose computing, packet processing, due to its memory-intensive nature, cannot rely exclusively on data-caching to eliminate the memory bottleneck completely.