A statistical static timing analysis considering correlations between delays
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
"AU: Timing Analysis Under Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Asymptotic probability extraction for non-normal distributions of circuit performance
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical delay computation considering spatial correlations
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Statistical timing analysis using bounds and selective enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Non-gaussian statistical parameter modeling for SSTA with confidence interval analysis
Proceedings of the 2006 international symposium on Physical design
Fast buffer insertion considering process variations
Proceedings of the 2006 international symposium on Physical design
Statistical clock tree routing for robustness to process variations
Proceedings of the 2006 international symposium on Physical design
Monte Carlo-Alternative Probabilistic Simulations for Analog Systems
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 43rd annual Design Automation Conference
Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty
Proceedings of the 43rd annual Design Automation Conference
A framework for statistical timing analysis using non-linear delay and slew models
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
An accurate sparse matrix based framework for statistical static timing analysis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A new statistical max operation for propagating skewness in statistical timing analysis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Microarchitecture parameter selection to optimize system performance under process variation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
Fast second-order statistical static timing analysis using parameter dimension reduction
Proceedings of the 44th annual Design Automation Conference
Non-linear statistical static timing analysis for non-Gaussian variation sources
Proceedings of the 44th annual Design Automation Conference
Extraction of statistical timing profiles using test data
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 44th annual Design Automation Conference
Statistical performance modeling and optimization
Foundations and Trends in Electronic Design Automation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A methodology for timing model characterization for statistical static timing analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Non-Gaussian statistical timing analysis using second-order polynomial fitting
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
VariaSim: simulating circuits and systems in the presence of process variability
ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems
Parameterized timing analysis with general delay models and arbitrary variation sources
Proceedings of the 45th annual Design Automation Conference
Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution
Proceedings of the 45th annual Design Automation Conference
Transistor-specific delay modeling for SSTA
Proceedings of the conference on Design, automation and test in Europe
Deep submicron interconnect timing model with quadratic random variable analysis
Proceedings of the conference on Design, automation and test in Europe
Incremental criticality and yield gradients
Proceedings of the conference on Design, automation and test in Europe
A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Adjustment-based modeling for statistical static timing analysis with high dimension of variability
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Statistical static timing analysis: A survey
Integration, the VLSI Journal
Timing analysis with compact variation-aware standard cell models
Integration, the VLSI Journal
Statistical ordering of correlated timing quantities and its application for path ranking
Proceedings of the 46th Annual Design Automation Conference
Statistical multilayer process space coverage for at-speed test
Proceedings of the 46th Annual Design Automation Conference
Non-Gaussian statistical timing analysis using second-order polynomial fitting
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast statistical analysis of process variation effects using accurate PLL behavioral models
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Adjustment-based modeling for timing analysis under variability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal test margin computation for at-speed structural test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pre-ATPG path selection for near optimal post-ATPG process space coverage
Proceedings of the 2009 International Conference on Computer-Aided Design
Timing model extraction for sequential circuits considering process variations
Proceedings of the 2009 International Conference on Computer-Aided Design
On hierarchical statistical static timing analysis
Proceedings of the Conference on Design, Automation and Test in Europe
Fast estimation of timing yield bounds for process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast statistical timing analysis for circuits with post-silicon tunable clock buffers
Proceedings of the International Conference on Computer-Aided Design
Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periods
Proceedings of the International Conference on Computer-Aided Design
Delay-correlation-aware SSTA based on conditional moments
Microelectronics Journal
Statistical Timing and Power Optimization of Architecture and Device for FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
An accurate sparse-matrix based framework for statistical static timing analysis
Integration, the VLSI Journal
Computation of joint timing yield of sequential networks considering process variations
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Order statistics for correlated random variables and its application to at-speed testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing and operational variations become more and more significant. Due to the nonlinearity of the mapping from variation sources to the gate/wire delay, the distribution of the delay is no longer Gaussian even if the variation sources are normally distributed. A novel quadratic timing model is proposed to capture the non-linearity of the dependency of gate/wire delays and arrival times on the variation sources. Systematic methodology is also developed to evaluate the correlation and distribution of the quadratic timing model. Based on these, a novel statistical timing analysis algorithm is propose which retains the complete correlation information during timing analysis and has the same computation complexity as the algorithm based on the canonical timing model. Tested on the ISCAS circuits, the proposed algorithm shows 10x accuracy improvement over the existing first order algorithm while no significant extra runtime is needed.