A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Statistical timing for parametric yield prediction of digital integrated circuits
Proceedings of the 40th annual Design Automation Conference
Timing Yield Estimation from Static Timing Analysis
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Fast statistical timing analysis handling arbitrary delay correlations
Proceedings of the 41st annual Design Automation Conference
Statistical timing analysis based on a timing yield model
Proceedings of the 41st annual Design Automation Conference
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
The impact of device parameter variations on the frequency and performance of VLSI chips
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical timing analysis using bounds and selective enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An exact algorithm for the statistical shortest path problem
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
The Challenges and Impact of Parasitic Extraction at 65 nm
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Refined statistical static timing analysis through
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Microarchitecture parameter selection to optimize system performance under process variation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Use of statistical timing analysis on real designs
Proceedings of the conference on Design, automation and test in Europe
A fully-automated desynchronization flow for synchronous circuits
Proceedings of the 44th annual Design Automation Conference
Statistical performance modeling and optimization
Foundations and Trends in Electronic Design Automation
Variations, margins, and statistics
Proceedings of the 2008 international symposium on Physical design
VariaSim: simulating circuits and systems in the presence of process variability
ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems
Statistical timing analysis of flip-flops considering codependent setup and hold times
Proceedings of the 18th ACM Great Lakes symposium on VLSI
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Statistical static timing analysis: A survey
Integration, the VLSI Journal
Timing analysis with compact variation-aware standard cell models
Integration, the VLSI Journal
Leakage reduction, delay compensation using partition-based tunable body-biasing techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Variation-aware supply voltage assignment for minimizing circuit degradation and leakage
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Timing margin evaluation with a simple statistical timing analysis flow
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Delay-correlation-aware SSTA based on conditional moments
Microelectronics Journal
A simple statistical timing analysis flow and its application to timing margin evaluation
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
A dynamic method for efficient random mismatch characterization of standard cells
Proceedings of the International Conference on Computer-Aided Design
Variation-aware supply voltage assignment for simultaneous power and aging optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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With an increasing trend in the variation of the primary parameters affecting circuit performance, the need for statistical static timing analysis (SSTA) has been firmly established in the last few years. While it is generally accepted that a timing analysis tool should handle parameter variations, the benefits of advanced SSTA algorithms are still questioned by the designer community because of their significant impact on complexity of STA flows. In this paper, we present convincing evidence that a path-based SSTA approach implemented as a post-processing step captures the effect of parameter variations on circuit performance fairly accurately. On a microprocessor block implemented in 90nm technology, the error in estimating the standard deviation of the timing margin at the inputs of sequential elements is at most 0.066 FO4 delays, which translates in to only 0.31% of worst case path delay.