Limits for automatic verification of finite-state concurrent systems
Information Processing Letters
Theory of linear and integer programming
Theory of linear and integer programming
Computability of recurrence equations
Theoretical Computer Science
The Organization of Computations for Uniform Recurrence Equations
Journal of the ACM (JACM)
Automatic verification of parameterized networks of processes
Theoretical Computer Science
An Automatic Generalization Method for the Inductive Proof of Replicated and Parallel Architectures
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
The d/dt Tool for Verification of Hybrid Systems
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Model Checking Guided Abstraction and Analysis
SAS '00 Proceedings of the 7th International Symposium on Static Analysis
Automatic Design of VLSI Pipelined LMS Architectures
PARELEC '00 Proceedings of the International Conference on Parallel Computing in Electrical Engineering
Proving parameterized systems: the use of pseudo-pipelines in polyhedral logic
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
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We propose a combination of heuristic methods to prove properties of control signals for regular systems defined by means of affine recurrence equations (AREs). We benefit from the intrinsic regularity of the underlying polyhedral model to handle parameterized systems in a symbolic way. Our techniques apply to safety properties. The general proof process consists in an iteration that alternates two heuristics. We are able to identify the cases when this iteration will stop in a finite number of steps. These techniques have been implemented in a high level synthesis environment based on the polyhedral model.