Exploiting Prediction to Reduce Power on Buses

Authors:
Victor Wen;Mark Whitney;Yatish Patel;John D. Kubiatowicz
Affiliations:
University of California at Berkeley;University of California at Berkeley;University of California at Berkeley;University of California at Berkeley
Venue:
HPCA '04 Proceedings of the 10th International Symposium on High Performance Computer Architecture
Year:
2004

Citing 0
Cited 3

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Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory

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Adaptive data compression for high-performance low-power on-chip networks

Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture

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Abstract

We investigate coding techniques to reduce the energy consumed by on-chip buses in a microprocessor. We explore several simple coding schemes and simulate them using a modified SimpleScalar simulator and SPEC benchmarks. We show an average of 35% savings in transitions on internal buses. To quantify actual power savings, we design a dictionary based encoder/decoder circuit in a 0.13µm process, extract it as a netlist, and simulate its behavior under SPICE. Utilizing a realistic wire model with repeaters, we show that we can break even at median wire length scales of less than 11.5mm at 0.13µ and project a break-even point of 2.7mm for a larger design at 0.07µ.