Parallelizing time with polynomial circuits

• Authors: Ryan Williams
• Venue: Proceedings of the seventeenth annual ACM symposium on Parallelism in algorithms and architectures
• Year: 2005

We study the relatively old problem of asymptotically reducing the runtime of serial computations with polynomial size Boolean circuits. To the best of our knowledge, no progress on this problem has been formally reported in the literature for general computational models, although we observe that early work of Chandra, Stockmeyer, and Vishkin implies the existence of non-uniform unbounded fan-in circuits of tO(1) size and O(tlog log n) depth, for time t Turing machine.We give an algorithmic size-depth tradeoff for parallelizing time t random access Turing machines, a model at least as powerful as logarithmic cost RAMs. Our parallel simulation yields logspace-uniform tO(1) size, O(t/logt) depth Boolean circuits having semi-unbounded fan-in gates. In fact, for appropriate d, uniform tO(1)2O(t/d) size circuits of depth O(d) can simulate time t. One corollary is that any log-cost time t RAM can be simulated by a log-cost CRCW PRAM using tO(1) processors and O(t/logt) time. This is a major improvement over previous parallel speedups, which could only guarantee an Ω(log t) speedup with an exponential number of processors.