A Multi-objective Genetic Algorithm for On-chip Real-time Optimisation of Word Length and Power Consumption in a Pipelined FFT Processor targeting a MC-CDMA Receiver

Authors:
Nasri Sulaiman
Affiliations:
University of Edinburgh
Venue:
EH '05 Proceedings of the 2005 NASA/DoD Conference on Evolvable Hardware
Year:
2005

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Cited 1

System-level modeling and multi-objective evolutionary design of pipelined FFT processors for wireless OFDM receivers

ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware

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Abstract

This paper presents a multi-objective Genetic Algorithm for on-chip real-time optimisation of word length and power consumption in a fixed-point pipelined Fast Fourier Transform (FFT) processor targeting on MC-CDMA receiver. The multi-objective GA is used to find solutions for the FFT coefficients which have optimum performance in term of signal to noise ratio (SNR) and power consumption. The results demonstrate that the GA can find solutions which are optimised for both objectives. Results also show that there is a significant reduction in power consumption while maintaining the SNR after the optimisation. Optimisation from 16-bit to 11-bit, results in power reduction of 6.6% and an average error of 0.69 dB.