Testing Distributed Systems Through Symbolic Model Checking
FORTE '07 Proceedings of the 27th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
The High Road to Formal Validation
ABZ '08 Proceedings of the 1st international conference on Abstract State Machines, B and Z
FM'06 Proceedings of the 14th international conference on Formal Methods
Fast and accurate strong termination analysis with an application to partial evaluation
WFLP'09 Proceedings of the 18th international conference on Functional and Constraint Logic Programming
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We study the formal verification of programs written in dSL, an extension of the standard ST language used to program industrial controllers. It proposes a trade off between industrial and formal verification worlds. The main advantage of dSL is to provide a transparent code distribution through low level communication mechanisms. The behavior of the synthesized distributed system can therefore be formally modeled, easily monitored and formally verified. The verification of a dSL program, realized with the Spin tool, is eased by the definition of a lattice of models linked with a simulation relation preserving next-free LTL formulae. We show that, although dSL is an industrial programming language, it gives the possibility to verify systems designed with it. We illustrate the benefit of our approach with a simple control system of two canal locks.