Optimistic intra-transaction parallelism on chip multiprocessors

Authors:
Christopher B. Colohan;Anastassia Ailamaki;J. Gregory Steffan;Todd C. Mowry
Affiliations:
Carnegie Mellon University, Pittsburgh, PA;Carnegie Mellon University, Pittsburgh, PA;University of Toronto, Toronto, Ontario, Canada;Carnegie Mellon University, Pittsburgh, PA
Venue:
VLDB '05 Proceedings of the 31st international conference on Very large data bases
Year:
2005

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Abstract

With the advent of chip multiprocessors, exploiting intra-transaction parallelism is an attractive way of improving transaction performance. However, exploiting intra-transaction parallelism in existing database systems is difficult, for two reasons: first, significant changes are required to avoid races or conflicts within the DBMS, and second, adding threads to transactions requires a high level of sophistication from transaction programmers. In this paper we show how dividing a transaction into speculative threads solves both problems---it minimizes the changes required to the DBMS, and the details of parallelization are hidden from the transaction programmer. Our technique requires a limited number of small, localized changes to a subset of the low-level data structures in the DBMS. Through this method of parallelizing transactions we can dramatically improve performance: on a simulated 4-processor chip-multiprocessor, we improve the response time by 36-74% for three of the five TPC-C transactions.