Impact of Soft Error Challenge on SoC Design

Authors:
Y. Zorian;V. A. Vardanian;K. Aleksanyan;K. Amirkhanyan
Affiliations:
Virage Logic Corporation;Virage Logic Yerevan Branch;Virage Logic Yerevan Branch;Virage Logic Yerevan Branch
Venue:
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Year:
2005

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Abstract

Soft errors are a major challenge to robust design. Conventionally, designs with high level requirements for reliability and availability required protection against soft errors. However, the scaling level reached with today's nanometer technologies is moving the soft error protection requirements to SoC designs for a wide range of applications. This paper discusses the soft error challenge, its implication on SoC design practices and possible approaches to create a robust SoC design.