Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology

Authors:
Animesh Datta;Saibal Mukhopadhyay;Swarup Bhunia;Kaushik Roy
Affiliations:
Purdue University;Purdue University;Purdue University;Purdue University
Venue:
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Year:
2005

Citing 0
Cited 2

Yield-Aware Cache Architectures

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
DEFCAM: A design and evaluation framework for defect-tolerant cache memories

ACM Transactions on Architecture and Code Optimization (TACO)

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Abstract

In nano-scaled technology large variations in process parameters produces wide delay spread in high performance circuit. In this paper we develop analytical models for yield prediction with respect to delay variation of pipeline design. We have addressed the converse problem of estimating the design space for individual pipe stages based on a target yield. For an example 4 stage pipelined circuit proposed analytical models are verified to predict yield within 2% of results obtained from Monte-Carlo Hspice simulation.