Distance-aware L2 cache organizations for scalable multiprocessor systems

Authors:
Sung Woo Chung;Hyong-Shik Kim;Chu Shik Jhon
Affiliations:
Processor Architecture Lab., SOC R&D Center, Samsung Electronics Co., Yongin, Gyeonggi-Do 449-711, South Korea;Department of Computer Science and Engineering, Chungnam National University, Daejeon 305-764, South Korea;School of Computer Science and Engineering, Seoul National University, Seoul 151-742, South Korea
Venue:
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable embedded systems: Synthesis, design and application
Year:
2005

Citing 14
Cited 0

Cache Operations by MRU Change

IEEE Transactions on Computers
Computer architecture: a quantitative approach

Computer architecture: a quantitative approach
A low-cost usage-based replacement algorithm for cache memories

ACM SIGARCH Computer Architecture News
The DASH prototype: implementation and performance

ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
The SPLASH-2 programs: characterization and methodological considerations

ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Optimal replacements in caches with two miss costs

Proceedings of the eleventh annual ACM symposium on Parallel algorithms and architectures
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers

ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Piranha: a scalable architecture based on single-chip multiprocessing

Proceedings of the 27th annual international symposium on Computer architecture
Limited Bandwidth to Affect Processor Design

IEEE Micro
The Effect of using State-Based Priority Information in a Shared-Memory Multiprocessor Cache Replacement Policy

ICPP '98 Proceedings of the 1998 International Conference on Parallel Processing
Utilization of Cache Area in On-Chip Multiprocessor

ISHPC '99 Proceedings of the Second International Symposium on High Performance Computing
MINT: A Front End for Efficient Simulation of Shared-Memory Multiprocessors

MASCOTS '94 Proceedings of the Second International Workshop on Modeling, Analysis, and Simulation On Computer and Telecommunication Systems
The Effectiveness of SRAM Network Caches in Clustered DSMs

HPCA '98 Proceedings of the 4th International Symposium on High-Performance Computer Architecture
Switch Cache: A Framework for Improving the Remote Memory Access Latency of CC-NUMA Multiprocessors

HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture

Quantified Score

Hi-index	0.00

Visualization

Abstract

In order to provide the scalability to the multiprocessor systems, it is important to keep the remote memory access time in bounds so that it does not impose much additional overhead as the system grows.In this paper, we suggest an LRU/distance-aware combined second-level(L2) cache for scalable CC-NUMA multiprocessors, which is composed of a traditional LRU cache and an additional distance-aware cache that maintains the distance information of individual cache block for replacement purposes. The LRU cache selects a victim using age information as it typically does, while the distance-aware cache does using distance information. Both work together to reduce effectively the overall distance the cache miss goes through by keeping long-distance blocks as well as recently used blocks. It has been observed that the proposed cache outperforms the traditional LRU cache by up to 28% in the execution time. It is also found to perform even better than an LRU cache of twice the size.