Low-power VLSI decoder architectures for LDPC codes
Proceedings of the 2002 international symposium on Low power electronics and design
Bit-interleaved coded modulation
IEEE Transactions on Information Theory
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
Multilevel codes: theoretical concepts and practical design rules
IEEE Transactions on Information Theory
IEEE Transactions on Information Theory
Hi-index | 0.00 |
We design multilevel coding (MLC) with a semi-bit interleaved coded modulation (BICM) scheme based on low density parity check (LDPC) codes. Different from the traditional designs, we joined the MLC and BICM together by using the Gray mapping, which is suitable to transmit the data over several equivalent channels with different code rates. To perform well at signal-to-noise ratio (SNR) to be very close to the capacity of the additive white Gaussian noise (AWGN) channel, random regular LDPC code and a simple semialgebra LDPC (SA-LDPC) code are discussed in MLC with parallel independent decoding (PID). The numerical results demonstrate that the proposed scheme could achieve both power and bandwidth efficiency.