Compiler-assisted power optimization for clustered VLIW architectures
Parallel Computing
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Current day system designs have stringent constraints on power dissipation without compromising on performance. In order to meet these often conflicting requirements, system designers require tools and methodologies that provide estimates of power dissipation at various levels of design hierarchy. Such tools also help architects evaluate power-performance trade-offs of various optimizations leading to low power, high performance system designs. Array structures such as caches, Branch Target Buffers (BTBs), tag arrays, register files etc. contribute to a significant portion of the total power in high performance designs. With increasing memory content in systems, their percentage contribution to total power dissipation is predicted to further increase in future technologies. This thesis proposes generic methodologies/models for estimation of power dissipation in array structures at different levels of the design hierarchy. At the transistor level, we propose a generic methodology to generate characterization based analytical power models for array structures. At the Register Transfer level (RT level), we propose an estimation tool named Implementation Dependent Array Power estimator (IDAP) that estimates power dissipation based on a high-level design description of the memory arrays. IDAP estimates both leakage and dynamic power dissipation in array structures. Finally, at the micro-architecture level, we developed a tool, eCACTI (enhanced CACTI), to (a) estimate the power dissipation in caches and (b) determine the optimal cache configuration that best meets the optimization criterion.