Design and implementation of ultra-low power pattern and sequence decoders

  • Authors:
  • Gert Cauwenberghs;Shantanu Chakrabartty

  • Affiliations:
  • The Johns Hopkins University;The Johns Hopkins University

  • Venue:
  • Design and implementation of ultra-low power pattern and sequence decoders
  • Year:
  • 2005

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Abstract

A key challenge in embedding pattern recognition intelligence onto ubiquitous sensing and communication interfaces in wireless integrated systems is to balance requirements on precision, complexity and power consumption in VLSI implementation. This dissertation investigates architectures for adaptive pattern recognition and sequence decoding, derived from statistical learning theory and Bayesian belief propagation on graphs, that lend naturally to efficient implementation in analog VLSI. Theoretical research in this area has resulted in forward decoding kernel machines (FDKM), a maximum a posteriori (MAP) based sequence decoder and has demonstrated state-of-art performance on various signal processing tasks in speech recognition and communications. The performance of FDKM depends on the discriminatory ability of an embedded large margin classifier. Investigation in this area has led to development of Gini-support vector machines, a sparse large margin classifier generating normalized output scores. These have been used extensively for image classification and voting networks. GiniSVM and FDKM systems have been optimized for accuracy and power dissipation and their architecture have been mapped onto a current-mode CMOS implementation. Non-volatile floating-gate MOS storage provides full analog programmability and trainability throughout all stages of the architecture. A calibration scheme, coupled with a chip-in-the-loop retraining procedure, cancels imprecision due to fabrication-induced mismatch in the analog circuit implementation. Calibration and retraining of a 3mm x 3mm SVM/FDKM chip fabricated in 0.5um CMOS technology, programmed for a speaker verification task, yields real-time recognition accuracy on par with floating-point software while dissipating sub-microwatt power. Applications include power-efficient smart sensors, implantable biomedical monitoring, biometric verification, human-computer interfaces, and adaptive iterative decoding communication systems.