Hardware support for code integrity in embedded processors
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Security extensions for integrity and confidentiality in embedded processors
Microprocessors & Microsystems
A hybrid hardware--software technique to improve reliability in embedded processors
ACM Transactions on Embedded Computing Systems (TECS)
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With the exponential growth of the number of interconnected computing platforms, computer security becomes a critical issue. As software continues to grow in size and complexity, so does the number of security vulnerabilities: According to the US-CERT Coordination Center, the number of vulnerabilities reported has grown from 171 in 1995 to 4,129 in 2002. One of the major security problems is the execution of unauthorized and potentially malicious code. This problem can be addressed at different levels, from more secure software and operating systems, down to solutions based on hardware support. The majority of the existing techniques tackle the problem of security flaws at the software level, lacking generality, often inducing prohibitive overhead in performance and cost, or generating a significant number of false alarms. On the other hand, a further increase in the number of transistors on a single chip will enable integrated hardware support for functions that were so far restricted to the software domain. Hardware-supported defense techniques have the potential to be more general and more efficient than solely software solutions. This dissertation proposes new architectural extensions to ensure trusted program execution in both high-end and embedded computing platforms. The eight proposed techniques have low performance overhead, low hardware complexity, and minimal or no compiler support.