Programmable logic core enhancements for high-speed on-chip interfaces
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A system-on-chip integrating a microprocessor, three embedded FPGA (eFPGA) and an eight portNetwork-On-Chip (NoC) is implemented in a 90nm CMOS technology. The system has been designed to execute complex multimedia applications by the use of hardware accelerators mapped to a reconfigurable platform based on a message-passing architecture. Computational kernels are mapped as hardware autonomous processes inside the eFPGAs or locally accelerated by the usage of dedicated microprocessor coprocessors. Each eFPGA on the system can be independently programmed and share logic with the others eFPGAs by intra-communication channels. The architecture is highly scalable since the eFPGA number can be controlled and the reconfigurable platform communication channels are based on a configurable NoC. The silicon area required by the system is 26mm2 in a 90nm CMOS process. 10x Speed Ups have been measured on a MP3 Player mapping example.