High-Performance FPGA-Based General Reduction Methods

Authors:
Gerald R. Morris;Ling Zhuo;Viktor K. Prasanna
Affiliations:
University of Southern California;University of Southern California;University of Southern California
Venue:
FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Year:
2005

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Abstract

FPGA-based floating-point kernels must exploit algorithmic parallelism and use deeply pipelined cores to gain a performance advantage over general-purpose processors. Inability to hide the latency of lengthy pipelines cansignificantly reduce the performance or impose unrealistic buffer requirements. Designs requiring reduction operations such as accumulation are particularly susceptible. In this paper we introduce two high-performance FPGA-based methods for reducing multiple sets of sequentially delivered floating-point values in optimal time without stalling the pipeline.