Recursive Filtering on a Vector DSP with Linear Speedup

Authors:
M. Van Der Horst;K. Van Berkel;J Lukkien;R. Mak
Affiliations:
Technische Universiteit Eindhoven, P.O. Box 5 13,5600 MB Eindhoven, Netherlands;Technische Universiteit Eindhoven, P.O. Box 5 13,5600 MB Eindhoven, Netherlands;Technische Universiteit Eindhoven, P.O. Box 5 13,5600 MB Eindhoven, Netherlands;Technische Universiteit Eindhoven, P.O. Box 5 13,5600 MB Eindhoven, Netherlands
Venue:
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Year:
2005

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Abstract

Vector DSPs, or SIMD DSPs, have received considerable attention recently, since they are considered to be a viable alternative for dedicated hardware in signal processingfor multi-media and wireless communication. It is possible to construct dedicated hardwarefor IIRjilters with a linear speedup, but because of their recursive nature these jilters are considered difficult to map efficiently on a vector DSP. The IIR programs for vector DSPs presented so far have their speedup bounded by the order of the filter. In this paper we present a program that has a linear speed up, in the sense that doubling the vector size will double the throughput. The program is a vectorization of the incremental block-state architecture. The speedup of this program is not bounded by the order of filter the and even works for low order filters. Besides strided memory access, no special processorfeatures are required by ourprogram. As a proof of conceptwe implemented it on the Philips EVP processor.