Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations
Transactions on High-Performance Embedded Architectures and Compilers I
Parallelization Approaches for Hardware Accelerators --- Loop Unrolling Versus Loop Partitioning
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
Constructing application-specific memory hierarchies on FPGAs
Transactions on high-performance embedded architectures and compilers III
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The COMPAAN/LAURA, [18] tool chain maps nested loop applications written in Matlab onto re-configurable platforms, such as FPGAs. COMPAAN rewrites the original Matlab application as a Process Network in which the control is parameterized and distributed. This control is given as parameterizedpolytopes that are expressed in of pseudo-linear expressions. These expressions cannot always be mapped eficiently onto hardware as they contain multiplication and integer division operations. This obstructs the data Jlow through the processes. Therefore, we present in this paper the Expression Compiler that eficiently maps pseudo-linear expressions onto a dedicated hardware path in such a way that the distributed and parameterized control never obstructs the data flow through processors. This compiler employs techniques like number theory axioms, method of difference, and predicated static single assignment code.