Low-power VLSI decoder architectures for LDPC codes
Proceedings of the 2002 international symposium on Low power electronics and design
Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
The capacity of low-density parity-check codes under message-passing decoding
IEEE Transactions on Information Theory
Errata for "good error-correcting codes based on very sparse matrices"
IEEE Transactions on Information Theory
Parallel turbo-sum-product decoder architecture for quasi-cyclic LDPC codes
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Optimal overlapped message passing decoding of quasi-cyclic LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-complexity high-speed decoder design for quasi-cyclic LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance evaluation and ASIC design of LDPC decoder for IEEE 802.11n
CCNC'09 Proceedings of the 6th IEEE Conference on Consumer Communications and Networking Conference
RTL design of LDPC decoder for IEEE802.11n WLAN
ISCIT'09 Proceedings of the 9th international conference on Communications and information technologies
An area efficient LDPC decoder using a reduced complexity min-sum algorithm
Integration, the VLSI Journal
Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders
Journal of Signal Processing Systems
Hi-index | 0.00 |
This paper proposes a partially-parallel LDPC decoder based on a high-ef?ciency message-passing algorithm. Our proposed partially-parallel LDPC decoder performs the column operations for bit nodes in conjunction with the row operations for check nodes. Bit functional unit with pipeline architecture in our LDPC decoder allows us to perform column operations for every bit node connected to each of check nodes which are updated by the row operations in parallel. Our proposed LDPC decoder improves the timing when the column operations are performed, accordingly it improves the message-passing efficiency within the limited number of iterations for decoding. We implemented the proposed partially-parallel LDPC decoder on an FPGA, and simulated its decoding performance. Practical simulation shows that our proposed LDPC decoder reduces the number of iterations for decoding, and it improves the bit error performance with a small hardware overhead.