Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm

  • Authors:
  • Kazunori Shimizu;Tatsuyuki Ishikawa;Takeshi Ikenaga;Satoshi Goto;Nozomu Togawa

  • Affiliations:
  • Graduate School of Information, Production and Systems, Waseda University;Graduate School of Information, Production and Systems, Waseda University;Graduate School of Information, Production and Systems, Waseda University;Graduate School of Information, Production and Systems, Waseda University;Dept. of Computer Science, Waseda University, Hibikino, Wakamatsuku, Kitakyushu-shi,Japan

  • Venue:
  • ICCD '05 Proceedings of the 2005 International Conference on Computer Design
  • Year:
  • 2005

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Abstract

This paper proposes a partially-parallel LDPC decoder based on a high-ef?ciency message-passing algorithm. Our proposed partially-parallel LDPC decoder performs the column operations for bit nodes in conjunction with the row operations for check nodes. Bit functional unit with pipeline architecture in our LDPC decoder allows us to perform column operations for every bit node connected to each of check nodes which are updated by the row operations in parallel. Our proposed LDPC decoder improves the timing when the column operations are performed, accordingly it improves the message-passing efficiency within the limited number of iterations for decoding. We implemented the proposed partially-parallel LDPC decoder on an FPGA, and simulated its decoding performance. Practical simulation shows that our proposed LDPC decoder reduces the number of iterations for decoding, and it improves the bit error performance with a small hardware overhead.