Parallel Logic Simulation of Million-Gate VLSI Circuits

Authors:
Lijuan Zhu;Gilbert Chen;Boleslaw K. Szymanski;Carl Tropper;Tong Zhang
Affiliations:
Rensselaer Polytechnic Institute, Computer Science Department;Rensselaer Polytechnic Institute, Computer Science Department;Rensselaer Polytechnic Institute, Computer Science Department;McGill University, School of Computer Science;Rensselaer Polytechnic Institute, ECSE
Venue:
MASCOTS '05 Proceedings of the 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems
Year:
2005

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Abstract

The complexity of today驴s VLSI chip designs makes veri fication a necessary step before fabrication. As a result, gate-level logic simulation has became an integral component of the VLSI circuit design process which verifies the design and analyzes its behavior. Since the designs constantly grow in size and complexity, there is a need for ever more ef?cient simulations to keep the gate-level logic veri- fication time acceptably small. The focus of this paper is an efficient simulation of large chip designs. We present the design and implementation of a new parallel simulator, called DSIM, and demonstrate DSIM驴s efficiency and speed by simulating a million gate circuit using different numbers of processors.