Simulating the power consumption of large-scale sensor network applications
SenSys '04 Proceedings of the 2nd international conference on Embedded networked sensor systems
IEEE Communications Magazine
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The current trend of computationally intensive applications such as audio capture, FFT, image sensing, motion detection, feature extraction and cepstrum calculations being ported to the sensor domain, alludes towards the need to handle copious amounts of data in comparison to rudimentary temperature and humidity sensing applications. Developing a split architecture based sensor platform is an effective and efficient methodology to reach the crucial goal of in-situ processing of data. Resulting in a direct reduction in the amount of information needed to be transmitted over the wireless links. The Split-Node-Architecture (SNA) which we develop addresses this very crucial aspect of sensor network design. The suitability of employing the SNA architecture is demonstrated by its performance metrics obtained by running a 128point FFT benchmark. The higher throughput, of the SNA architecture enables faster data processing upto 24 times that of the Atmel AVR architecture (MICA). Additionally a 29% improvement in power efficiency vis a vis popular sensor platforms, tilts the scales unambiguously in favor of the SNA. The low power consumption of the Co-S module, a part of SNA, results in savings upto 6uJ per 128 point FFT operation when compared to the Stargate (Intel PXA 255).