On bounding the delay of a critical path
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
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With process variations, timing behavior may vary from chip to chip. This paper investigates the problem of generating test patterns to cover potentially diverse worst-case timing corners. We focus the work on a specific problem formulation where the delay of a path can be affected by k aggressors. We demonstrate that the search space for such a problem can be quite complex. We study various methods to guide the test generation. We show that with different chips having different worst-case corners, it may not be affordable to search for the tests to expose all these corners. Experimental results are presented to explain the problem formulation, the test generation methods, and the limitation on what we can achieve for solving the problem.