DRACO: optimized CC-NUMA system with novel dual-link interconnections to reduce the memory latency

Authors:
Hyo-Joong Suh;Sung Woo Chung
Affiliations:
The Catholic University of Korea;Processor Architecture Lab., Samsung Electronics
Venue:
MEDEA '04 Proceedings of the 2004 workshop on MEmory performance: DEaling with Applications , systems and architecture
Year:
2004

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Abstract

The performances of multiprocessor systems mainly rely on the processor clock speed and the memory latency. As the processors speed up rapidly, the memory latency becomes a major performance bottleneck in multiprocessor systems. In this paper, we propose a dual-link interconnection topology and its effective routing scheme to reduce the remote memory latency on the interconnection network. It can be applied at a same implementation cost as traditional bi-directional ring systems. We compare the performance of the proposed system to that of the traditional bi-directional ring-based system and toroidal mesh-based system. By simulations, it is shown that the proposed system outperforms the traditional bi-directional ring-based system by 42~101 % and excels the toroidal mesh-based system by 4~14%.