Application of design for verification with concurrency controllers to air traffic control software

  • Authors:

  • Aysu Betin-Can;Tevfik Bultan;Mikael Lindvall;Benjamin Lux;Stefan Topp

  • Affiliations:

  • University of California, Santa Barbara, CA;University of California, Santa Barbara, CA;Fraunhofer Center for Experimental Software Engineering, College Park, MD;Fraunhofer Center for Experimental Software Engineering, College Park, MD;Fraunhofer Center for Experimental Software Engineering, College Park, MD

  • Venue:
  • Proceedings of the 20th IEEE/ACM international Conference on Automated software engineering
  • Year:
  • 2005

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Abstract

We present an experimental study which demonstrates that model checking techniques can be effective in finding synchronization errors in safety critical software when they are combined with a design for verification approach. We apply the concurrency controller design pattern to the implementation of the synchronization operations in Java programs. This pattern enables a modular verification strategy by decoupling the behaviors of the concurrency controllers from the behaviors of the threads that use them using interfaces specified as finite state machines. The behavior of a concurrency controller can be verified with respect to arbitrary numbers of threads using infinite state model checking techniques, and the threads which use the controller classes can be checked for interface violations using finite state model checking techniques. We present techniques for thread isolation which enables us to analyze each thread in the program separately during interface verification. We conducted an experimental study investigating the effectiveness of the presented design for verification approach on safety critical air traffic control software. In this study, we first reengineered the Tactical Separation Assisted Flight Environment (TSAFE) software using the concurrency controller design pattern. Then, using fault seeding, we created 40 faulty versions of TSAFE and used both infinite and finite state verification techniques for finding the seeded faults. The experimental study demonstrated the effectiveness of the presented modular verification approach and resulted in a classification of faults that can be found using the presented approach.