Automatic verilog code generation through grammatical evolution

Authors:
Ulya R. Karpuzcu
Affiliations:
Istanbul Technical University, Maslak, Istanbul, Turkey
Venue:
GECCO '05 Proceedings of the 7th annual workshop on Genetic and evolutionary computation
Year:
2005

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Abstract

This work aims to investigate the automatic generation of Verilog code, representing digital circuits through Grammatical Evolution (GE). Preliminary tests using a simple full adder generation problem have been performed.