An optimization strategy for low energy and high performance for the on-chip interconnect signalling
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
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As the technology scales down, the increased wire aspect ratio and the reduced spacing between the individual wires within a bus result in increased crosscoupling capacitances. This increases crosstalk noise and power dissipation particularly in wide data buses. We propose an efficient encoding scheme that eliminates correlated switching (coupling transitions) in 4-bit busses and also minimizes self-transitions among the wires in these data busses. Wider data busses are implemented using these 4-bit bus blocks.