Mumford and Shah Functional: VLSI Analysis and Implementation

Authors:
Maurizio Martina;Guido Masera
Affiliations:
IEEE;IEEE
Venue:
IEEE Transactions on Pattern Analysis and Machine Intelligence
Year:
2006

Citing 12
Cited 0

Visual reconstruction with discontinuities using variational methods

Image and Vision Computing
A multiscale algorithm for image segmentation by variational method

SIAM Journal on Numerical Analysis
A distributed memory unstructured gauss-seidel algorithm for multigrid smoothers

Proceedings of the 2001 ACM/IEEE conference on Supercomputing
Diffusion Snakes: Introducing Statistical Shape Knowledge into the Mumford-Shah Functional

International Journal of Computer Vision
Variational Restoration and Edge Detection for Color Images

Journal of Mathematical Imaging and Vision
Formal Derivation of an Efficient Parallel 2-D Gauss-Siedel Method

IPPS '92 Proceedings of the 6th International Parallel Processing Symposium
On Designing a Systolic Network for the Resolution of Linear Systems Using the " Gauss-Seidel " Method

AICCSA '01 Proceedings of the ACS/IEEE International Conference on Computer Systems and Applications
Self-Adaptive Regularization

IEEE Transactions on Pattern Analysis and Machine Intelligence
Motion Competition: A Variational Approach to Piecewise Parametric Motion Segmentation

International Journal of Computer Vision
Combining performance aspects of irregular gauss-seidel via sparse tiling

LCPC'02 Proceedings of the 15th international conference on Languages and Compilers for Parallel Computing
Active contours without edges

IEEE Transactions on Image Processing
Multichannel blind iterative image restoration

IEEE Transactions on Image Processing

Quantified Score

Hi-index	0.14

Visualization

Abstract

This paper describes the analysis of the Mumford and Shah functional from the implementation point of view. Our goal is to show results in terms of complexity for real-time applications, such as motion estimation based on segmentation techniques, of the Mumford and Shah functional. Moreover, the sensitivity to finite precision representation is addressed, a fast VLSI architecture is described, and results obtained for its complete implementation on a 0.13 \mu\rm m standard cells technology are presented.