Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Robust analog/RF circuit design with projection-based posynomial modeling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Worst-case analysis and optimization of VLSI circuit performances
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast interval-valued statistical interconnect modeling and reduction
Proceedings of the 2005 international symposium on Physical design
Proceedings of the 42nd annual Design Automation Conference
Correlation-aware statistical timing analysis with non-gaussian delay distributions
Proceedings of the 42nd annual Design Automation Conference
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model
Proceedings of the 42nd annual Design Automation Conference
Robust analog/RF circuit design with projection-based posynomial modeling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Speed binning aware design methodology to improve profit under parameter variations
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Probabilistic evaluation of solutions in variability-driven optimization
Proceedings of the 2006 international symposium on Physical design
SACI: statistical static timing analysis of coupled interconnects
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Efficient statistical capacitance variability modeling with orthogonal principle factor analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Projection-based performance modeling for inter/intra-die variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Non-gaussian statistical interconnect timing analysis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
Statistical analysis of full-chip leakage power considering junction tunneling leakage
Proceedings of the 44th annual Design Automation Conference
Non-linear statistical static timing analysis for non-Gaussian variation sources
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 44th annual Design Automation Conference
Statistical performance modeling and optimization
Foundations and Trends in Electronic Design Automation
Statistical analysis of RF circuits using combined circuit simulator-full wave field solver approach
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Parametric variability analysis for multistage analog circuits using analytical sensitivity modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design Considerations for High Performance RF Cores Based on Process Variation Study
Journal of Electronic Testing: Theory and Applications
Non-Gaussian statistical timing analysis using second-order polynomial fitting
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
Profit aware circuit design under process variations considering speed binning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical static timing analysis: A survey
Integration, the VLSI Journal
Proceedings of the 46th Annual Design Automation Conference
Efficient design-specific worst-case corner extraction for integrated circuits
Proceedings of the 46th Annual Design Automation Conference
Statistical reliability analysis under process variation and aging effects
Proceedings of the 46th Annual Design Automation Conference
Non-Gaussian statistical timing analysis using second-order polynomial fitting
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Full-chip leakage analysis for 65nm CMOS technology and beyond
Integration, the VLSI Journal
Stochastic analog circuit behavior modeling by point estimation method
Proceedings of the 2011 international symposium on Physical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient method for analyzing on-chip thermal reliability considering process variations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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While process variations are becoming more significant with each new IC technology generation, they are often modeled via linear regression models so that the resulting performance variations can be captured via normal distributions. Nonlinear (e.g. quadratic) response surface models can be utilized to capture larger scale process variations; however, such models result in non-normal distributions for circuit performance which are difficult to capture since the distribution model is unknown. In this paper we propose an asymptotic probability extraction method, APEX, for estimating the unknown random distribution when using nonlinear response surface modeling. APEX first uses a binomial moment evaluation to efficiently compute the high order moments of the unknown distribution, and then applies moment matching to approximate the characteristic function of the random circuit performance by an efficient rational function. A simple statistical timing example and an analog circuit example demonstrate that APEX can provide better accuracy than Monte Carlo simulation with 10 samples and achieve orders of magnitude more efficiency. We also show the error incurred by the popular normal modeling assumption using standard IC technologies.