Static statistical timing analysis for latch-based pipeline designs

Authors:
Mango C.-T. Chao;Li-C Wang;Kwang-Ting Cheng;S. Kundu
Affiliations:
Dept. of ECE, California Univ., Santa Barbara, CA, USA;Dept. of ECE, California Univ., Santa Barbara, CA, USA;Dept. of ECE, California Univ., Santa Barbara, CA, USA;Intel Corporation, Austin, Texas
Venue:
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Year:
2004

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Abstract

A latch-based timing analyzer is an essential tool for developing high-speed pipeline designs. As process variations increasingly influence the timing characteristics of DSM designs, a timing analyzer capable of handling process-induced timing variations for latch-based pipeline designs becomes in demand. In this work, we present a static statistical timing analyzer, STAP, for latch-based pipeline designs. Our analyzer propagates statistical worst-case delays as well as critical probabilities across the pipeline stages. We present an efficient method to handle correlations due to re-convergent fanouts. We also demonstrate the impact of not including the analysis of reconvergent fanouts in latch-based pipeline designs. Comparing to a Monte-Carlo based timing analyzer, our experiments show that STAP can accurately evaluate the critical probability that a design violates the timing constraints under a given statistical timing model. The runtime comparison further demonstrates the efficiency of our STAP.