Studying a GALS FPGA architecture using a parameterized automatic design flow
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
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The performance of FPGAs is suffering from interconnect delays, especially the delays of the long wires which can be more than 10ns in large FPGAs. We have proposed the GAPLA: a Globally Asynchronous Locally Synchronous (GALS) FPGA architecture to deal with this problem. In GAPLA architecture, the whole FPGA area is divided into locally synchronous blocks wrapped with asynchronous I/O interfaces. Interconnections inside each synchronous block are local and fast. The long interconnections between synchronous blocks only come into picture when there are asynchronous communications. In this paper, we focus on the CAD tools designed for the GAPLA architecture. Starting from a behavioral circuit description, a design is first partitioned into smaller modules where each module can fit into one synchronous block. Then an As-Soon-As-Possible scheduler (other scheduler can also be applied) is used to schedule each module. After scheduling, control signals of the asynchronous communications are added to each module since the communication timing is now known in the scheduled design. Each module is then synthesized and mapped into a synchronous block using existing CAD tools for synchronous FPGAs. A module mapping process is used to find the implementation location for each module. Experimental results show that applications could run upto 2 times faster on the GAPLA FPGA compared to the synchronous FPGA counterparts.