Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core

  • Authors:
  • Partha Biswas;Sudarshan Banerjee;Nikil Dutt;Paolo Ienne;Laura Pozzi

  • Affiliations:
  • University of California at Irvine;University of California at Irvine;University of California at Irvine;Ecole Polytechnique Fédérale de Lausanne;Ecole Polytechnique Fédérale de Lausanne

  • Venue:
  • VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
  • Year:
  • 2006

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Abstract

Performance of applications can be boosted by executing application-specificInstruction Set Extensions (ISEs) on a specialized hardware coupled with a processor core. Many commercially available customizable processors have communication overheads in their interface with the specialized hardware. However, existing ISE generation approaches have not considered customizable processors that have communication overheads at their interface. Furthermore, they have not characterized the energy benefits of such ISEs. We present a soft-processor customization framework that takes an input 'C' application and realizes a customized processor capturing the microarchitectural details of its interface with the specialized unit. We are able to accurately measure the speedup, energy, power and code size benefits of our ISE approach on a real system implementation by applying the design flow to a popular Xilinx Microblaze soft-processor core synthesized for four real-life applications. We show that only one large ISE per application is sufficient to get an average 1.41脳 speedup over pure software execution in spite of incurring communication overheads in the ISE implementation. We also observe a simultaneous savings in energy (up to 40%) and power (up to 12% peak power reduction) with this increased performance.