Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation

  • Authors:

  • Aswath Oruganti;Nagarajan Ranganathan

  • Affiliations:

  • University of South Florida;University of South Florida

  • Venue:
  • VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
  • Year:
  • 2006

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Abstract

The noise sensitivity of low power circuits is rapidly increasing with the increasing levels of process variability and uncertainty. In this work, we study the problem of leakage power minimization in dual-Vdd and dual-Vth designs in the presence of significant Vth variation. The impact of the uncertainty in Vth on leakage power and timing are studied through probabilistic analytical models. We develop probabilistic models for timing slack and leakage power considering threshold variations with the objective of achieving an optimal selection of Vth. An analysis of the models indicate that, in the presence of variability, the value of the second Vth must be about 30mv higher than the Vth value obtained without considering variability. We show that our proposed method for the selection of Vth yields the lowest leakage power ratio of the dual-Vdd and dual-Vth versus the single-Vdd and single-Vth designs. In addition, the proposed models can be used to determine the ideal values for the second Vdd and Vth values in the context of variability for a variety of process conditions.