Properties Incompleteness Evaluation by Functional Verification
IEEE Transactions on Computers
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Verification of circuit description by means of model checking means to write propositions, expressed in some temporal logic, expected to be true on the implementation according to the specification content. Completeness of the set of written properties is still an open problem. We propose a practical approach to the property coverage metrics definition based on fault injection; a combination of model checking, fault simulation and emulation allows to reduce the coverage measure to an affordable task. The application of these three different technologies is illustrated on a real example, on which it leads to the discovery of a missing property in a property set formerly trusted to be complete.