Developing mesochronous synchronizers to enable 3D NoCs
Proceedings of the conference on Design, automation and test in Europe
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In this paper we present the circuit implementation of a new asynchronous delay-insensitive on-chip link structure, where two modules placed on the opposite sides of the link can exchange data simultaneously. Unlike the conventional delay-insensitive dual-rail link which requires 2N + 1 interconnects to transfer N-data bit, N +1 interconnects are required in this design. As two transceivers can access simultaneously the same physical interconnect the number of required interconnects halves compared to bidirectional transfer based on two separate unidirectional dual-rail links.This makes the link cost effective for future SoC. The transceiver circuits are designed using multiplevalued current-mode logic, linear summation is implemented by wiring without active devices simplifying the resulting circuitry. By using 110mV voltage swing the power consumption of the link is 8.32mW for 689ps propagation delay and 5mm interconnect length. Some of the potential application areas of this link are between locally clocked modules in GALS system, between routers of NoC nodes, and in adaptive and reconfigurable system where feedback information is crucial. The circuit is designed and simulated using Cadence Analog Spectre with 0.13um CMOS technology.