A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes

Authors:
Erwan PIRIOU;Christophe JEGO;Patrick ADDE;Michel JEZEQUEL
Affiliations:
GET/ENST Bretagne, CNRS TAMCIC UMR 2872 , Brest, France;GET/ENST Bretagne, CNRS TAMCIC UMR 2872 , Brest, France;GET/ENST Bretagne, CNRS TAMCIC UMR 2872 , Brest, France;GET/ENST Bretagne, CNRS TAMCIC UMR 2872 , Brest, France
Venue:
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Year:
2006

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Abstract

In this paper, the first flexible architecture dedicated to block turbo decoders is presented. The major innovation concerns the component code that is used by the block turbo code. In fact, our architecture is able to decode BCH and Reed-Solomon codes with single or double correction power. To the authors' knowledge, this is the first architecture implementing Reed-Solomon block turbo codes. This approach makes it possible to select the block turbo decoder architecture using optimum component codes in any circumstance. Our flexible elementary SISO decoder is dedicated to extended binary BCH codes (32,26) and (32,21) and to non-extended Reed-Solomon codes (31,29) and (31,27). Experimentation has been done on a Stratix-based NIOS development board.