High Quality Uniform Random Number Generation for Massively Parallel Simulations in FPGAS

Authors:
David B. Thomas;Wayne Luk
Affiliations:
Imperial College;Imperial College
Venue:
RECONFIG '05 Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05) on Reconfigurable Computing and FPGAs
Year:
2005

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Cited 1

An FPGA implementation of a parallelized MT19937 uniform random number generator

EURASIP Journal on Embedded Systems - FPGA supercomputing platforms, architectures, and techniques for accelerating computationally complex algorithms

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Abstract

This paper details the design and implementation of three uniform random number generators for use in massively parallel simulations in FPGAs. The three different generators are tailored to make use of three different types of hardware resource: logic, RAM, and DSP blocks. This allows the random number generator to be fitted into resources left-over after the main application has been written. The three generators all pass the most stringent empirical statistical tests for randomness, and all have periods appropriate for long running simulations.