An FPGA-Based Coprocessor for the SPHINX Speech Recognition System: Early Experiences

Authors:
Guillermo Marcus;Juan A. Nolazco-FIores
Affiliations:
Universität Mannheim;ITESM
Venue:
RECONFIG '05 Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05) on Reconfigurable Computing and FPGAs
Year:
2005

Citing 0
Cited 2

An FPGA implementation of the local global graph-based voice biometric authentication scheme

DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
Domain-Specific Optimization of Signal Recognition Targeting FPGAs

ACM Transactions on Reconfigurable Technology and Systems (TRETS)

Quantified Score

Hi-index	0.12

Visualization

Abstract

A FPGA based hardware coprocessor for the SPHINX Speech Recognition System is presented. The coprocessor operates at 66MHz and implements a critical part of the Baum-Welch Algorithm to assist in the Gaussian probability calculations, currently with a peak performance of 264 MFlops. Results are presented in comparison with a Xeon 2.66GHz computer and a similar ASIC project, together with guidelines for future development.