Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures

  • Authors:

  • Rakesh Kumar;Keith Farkas;Norman P Jouppi;Partha Ranganathan;Dean M Tullsen

  • Affiliations:

  • -;-;-;-;-

  • Venue:
  • IEEE Computer Architecture Letters
  • Year:
  • 2002

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Abstract

This paper proposes a single-ISA heterogeneous multi-core architecture as a mechanism to reduce processor power dissipation. It assumes a single chip containing a diverse set of cores that target different performance levels and consume different levels of power. During an application's execution, system software dynamically chooses the most appropriate core to meet specific performance and power requirements. It describes an example architecture with five cores of varying performance and complexity. Initial results demonstrate a five-fold reduction in energy at a cost of only 25% performance.