Locality-Based Online Trace Compression
IEEE Transactions on Computers
Automatic Generation of High-Performance Trace Compressors
Proceedings of the international symposium on Code generation and optimization
The VPC Trace-Compression Algorithms
IEEE Transactions on Computers
TCgen 2.0: a tool to automatically generate lossless trace compressors
ACM SIGARCH Computer Architecture News
An efficient single-pass trace compression technique utilizing instruction streams
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Prediction and trace compression of data access addresses through nested loop recognition
Proceedings of the 6th annual IEEE/ACM international symposium on Code generation and optimization
Scalable Communication Trace Compression
CCGRID '10 Proceedings of the 2010 10th IEEE/ACM International Conference on Cluster, Cloud and Grid Computing
Hardware-based data value and address trace filtering techniques
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
| Hi-index | 0.01 |
Trace-driven simulation has long been used in bothprocessor and memory studies. The large size of traces motivateddifferent techniques for trace reduction. These techniques oftencombine standard compression algorithms with trace-specificsolutions, taking into account the tradeoff between reduction inthe trace size and simulation slowdown due to decompression.This paper introduces SBC, a new algorithm for instruction anddata address trace compression based on instruction streams. Theproposed technique significantly reduces trace size andsimulation time, and it is orthogonal to general compressionalgorithms. When combined with gzip, SBC reduces the size ofSPEC CPU2000 traces 94-71968 times.