AC IO Loopback Design for High Speed uProcessor IO Test

Authors:
Benoit Provost;Chee How Lim;Mo Bashir;Ali Muhtaroglu;Tiffany Huang;Kathy Tian;Mubeen Atha;Cangsang Zhao;Harry Muljono
Affiliations:
Intel Corporation. Hillsboro, OR, USA;Intel Corporation. Hillsboro, OR, USA;Intel Corporation. Hillsboro, OR, USA;Intel Corporation. Hillsboro, OR, USA;Intel Corporation. Santa Clara, CA, USA;Intel Corporation. Santa Clara, CA, USA;Intel Corporation. Santa Clara, CA, USA;Intel Corporation. Santa Clara, CA, USA;Intel Corporation. Santa Clara, CA, USA
Venue:
ITC '04 Proceedings of the International Test Conference on International Test Conference
Year:
2004

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Abstract

This paper presents the next generation AC IO Loopback design for two Intel processor architectures. Both designs detect I/O defects with 20 ps resolution and 50 ps jitter for up to 800 MHz bus speed. Even though the implementations differ in some aspects to accommodate two different bus architectures, the same prudent considerations for high speed operation, minimum test inaccuracy, and low implementation costs apply to both.