A Reconfigurable Processor Infrastructure for Accelerating Java Applications
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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In this paper, we present our compiler infrastructure, called Jaguar for Java reconfigurable computing. The Jaguar compiler translates compiled Java methods, i.e. sequence of bytecodes into Verilog synthesizable code modules with exploiting the maximum operational parallelism in applications. Our compiler infrastructure consists of two major components: One is a compiler to generate synthesizable Verilog codes from Java applications, which performs full compilation passes, such as bytecode parsing, intermediate representation (IR) construction, program analysis, optimization, and code emission. The other component is the Java Virtual Machine (JVM), which provides Java execution environment to compiler-generated hardware. The JVM runs on a host processor and the generated hardware does on FPGA. Differently from previous work, our compiler infrastructure is a complete and solid solution for Java reconfigurable computing. We present how to design our compiler framework. Our infrastructure improves the performance by 66% on average and by up to 174% in measured benchmarks. Also we discuss the performance issues in detail, especially focusing on overhead of interactions between JVM and Jaguar hardware.